A Quick and Easy GPS-Controlled Frequency Standard

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he more you become involved in home construction and design, the more necessary it is to have available stable, reliable and precise frequency measuring equipment, both to evaluate home construction products, and to ensure compliance with band plans and licensing requirements.  Some amateur modes, such as qrss, require extreme stability and precision if the the operator is to have confidence in his or her public presence on-air.  Many qrss operators use rubidium standards to control their rigs, although strictly speaking a good ovened crystal will give adequate stability while leaving the question of calibration unresolved.  So a quick and easy frequency standard which provides reliable frequency calibration is highly desirable.  In the UK the LF station MSF at 60kHz (located at Anthorn, Cumbria)  is intended to be a national resource for frequency and timing calibration, and is maintained as such by the National Physical Laboratory to a very high order of precision.  The station at G4OEP has relied on this standard for many years, and I have a system which phase-locks a 2MHz VXO to the 60kHz carrier, the 2MHz output serving as a timebase for a home brew frequency counter with 1Hz resolution in the HF region.  Also, my phase-locked clocks can be checked by an error-logger which compares the 1Hz pulses from the clocks with the standard UTC 1Hz modulation of the MSF signal.  These standardisation systems have proved to be reliable and extremely useful over a period of at least 2 decades.

The only reason for dissatisfaction with MSF is that it is too often, and too unpredictably off-air.  GPS therefore seems a worthwhile option as an alternative.  Most easily-available GPS receiver modules include a 1Hz output with a claimed precision of parts in 10^11.  Technically, locking an HF oscillator to a 1Hz standard seems at first sight a tricky task likely to raise several problems related to lock-time, phase noise, etc.  But the technique illustrated here has proved to be surprisingly quick and easy, and although I have not evaluated performance rigorously, it is clear that this exceedingly simple technique is useful.  Lock can be achieved in about 3 or 4 minutes after the receiver itself has stabilised. I have checked correct operation by locking the system to the 1Hz gating pulse of a frequency counter, while comparing the 4MHz output against the crystal oscillator of the counter (from which the gating pulse is derived by a chin of frequency dividers).  
There is no perceptible phase wobble relative to the free-running crystal even when compared on a dual-channel scope with a 20ns/div timebase.  However, the lock can be momentarily disturbed by abrupt changes of temperature, so it is best to enclose the crystal, and protect it from drafts.  A refinement would be to oven the crystal, but this would significantly increase the complexity, and is hardly worth-while. 
The system is more than adequate as a timebase for a frequency counter, and the purity of tone of the harmonics in the HF band indicates that it is also good for even the most demanding of amateur requirements.  In short, the technique is quick, simple, and highly recommended.
A PIC 16F627 is used to lock a 2MHz crystal although other frequencies can also be used. The internal T0 counter and the pulse-width modulation (PWM) module of the PIC are exploited.  The technique is as follows:

T0 is an 8-bit counter which, when enabled, increments at a rate set by the internal cpu clock frequency.  T0 creates an interrupt each time the counter register overflows.  The interrupt service routine (isr) preloads the counter with a fixed number (nominally 6, but see below for details) every time T0 overflows so that successive overflows occur every 250 counts (equivalent to cpu clock cycles).  The cpu clock is derived from an external 2MHz VXO, which is tuned over a narrow range by a varactor diode.  Inside the PIC, the external clock input is divided by 4 to provide the cpu clock.  The result of this is that the internal clock is at 500kHz, and interrupts occur every 500us (2kHz).   Because the T0 counter register runs continuously, its contents represent a running total of  quarter-milliseconds, mod 250, and this is a continuous count of the VXO cycles, divided by 1,000.  






The GPS 1Hz pulse is applied to the external interrupt input to the PIC. These interrupts are not enabled, but the external interrupt flag is monitored in a loop in the main program, and each time a rising edge of the GPS 1Hz occurs, the contents of T0 are read.  Because T0 is cumulative, its contents can be interpreted as a phase error. Since T0 counts mod 250, and 500kHz is an integer multiple of this, T0 will have the same value each second if the 2MHz VXO is exactly on-frequency.  If the VXO is running at too high a frequency, the read value of T0 will steadily increase, while if it is running slow, the T0 count will steadily decrease.  

To complete the frequency control loop, the value of T0, as read each second, is written to the register of the PIC's PWM module which controls the period  of the PWM waveform,
the high phase (duty cycle) being fixed, set in the initialisation routine of the software.  The PWM output is filtered to recover its dc component, amplified, and then applied to the VXO as a frequency control input.  If T0 increases, for example (due to the clock oscillator running fast) the average PWM output voltage falls, the capacitance of the varactor increases, and the VXO frequency is corrected in the required downward direction.  

An alternative way of creaing the control signal is to complement the T0 count, and use the result to control the high phase of the PWM output, the period remaining fixed.  Either technique will work, but I have settled on the first for reasons discussed below.  

Theoretically the system could lock to any frequency (f) which satisfies the equation f = 1000*Ni where Ni is an integer - the number of interrupts each second.(2000 in this application).  The nearest alternative frequencies are thus 2MHz +/- 1kHz.  A crystal will not drift by as much as 1kHz, so there is no possibility of a false lock.  Clearly other frequencies can be generated without modification, except a change of crystal, provided the target frequency is an integral number of kHz.  The system has been tested with a 4MHz VXO, and I can confirm that it works well at this frequency as well, without any change in the software.  The capture transient can be expected to be slightly different at different output frequencies.

I am not certain whether it is correct to describe this as a phase-locked loop (pll). In many respects it is one, particularly since the control signal represents a cumulative phase error.  However, the phase of the locked output is not directly linked to the rising edge of the 1Hz standard, since a 4-cycle error in the output must occur before corrective action is taken (i.e. before the T0 counter increments or decrements by one count).  In practice the dual-beam display (described above) shows that when the system is locked there is a constant phase relationship between the output and the standard input, so perhaps one should be satisfied with that !


The loop filter of any pll system is crucial to satisfactory operation.  In this design the filter consists of  a 100uF tantalum capacitor with a 220kOhm resistor  in a first-order LPF configuration.  A 10k resistor is added in series with the cap (between the cap and ground) to increase damping.  Damping is not optimal, but is adequate (see right; this shows the locking transient following a completely cold start, including the capture time of the GPS receiver).

An op-amp amplifier with a voltage gain of about 3 is included in the loop.  In my implementation of the design, the op-amp is powered from a MAX232 chip which provides +/-9v supplies from a single 5v input. This allows a useful but only moderate increase in the range of the control voltage (from about 5v maximum from the PWM module, to about 8v).  Under these conditions it is possible for the op-amp to saturate, so the average of the PWM output (i.e. its filtered, dc value) must always be in a rather low range, well below its maximum value of 5v.  This means that if the high phase of the PWM signal is controlled by T0, there will be a rather coarse, low-resolution control, whereas if T0 controls the PWM period instead, T0 can range up to its maximum value (256) without causing the op-amp to saturate.  This allows better resolution, and has therefore been adopted.  The steady-state value of T0, and of the control voltage is adjusted by a trimmer in the VXO.  

The software can be downloaded using this link.  Astonishingly, the basic system uses just 49 bytes of assembled opcodes, but if the lock indicator is added this increases to 56 bytes.  To my mind this system is amazingly simple and efficient.

Software notes. The software is so simple that the explanation given above is adequate.  However, there is one subtlety that  is worth mentioning in case anyone feels inclined to meddle, or to apply the principle in another context:-

Ideally, when T0 reaches a value of 255 and overflows, it should be immediately reset to 6 so that the counting cycle repeats after 250 increments.  However, the inherent interrupt latency, and the execution of the isr instructions prior to the write to T0 introduce a delay, so that it is impossible to reset T0 immediately.  In this isr, the total delay amounts to 12 cpu clock cycles (including 2 NOPs).  So T0 is pre-loaded with 18 instead of just 6.  The NOPs are included to make the total latency an integral number of  T0 increments when the T0 prescaler is used at its 2:1 or 4:1 settings.  These were experimented with, but the 1:1 setting finally used.  If  the NOPs are deleted, the pre-load value must be reduced to 16.